Low-power design has become a critical requirement in modern semiconductor SoCs, especially for battery-powered devices, wearables, automotive ECUs, AI accelerators, and mobile processors. Among the most widely used low-power techniques, clock gating and power gating stand out as essential pillars for optimizing dynamic and leakage power.

Understanding how to implement these techniques correctly—at the RTL level, in the physical design backend, and during functional and power-aware verification—is essential for every VLSI engineer. This in-depth guide explains the complete flow, best practices, challenges, and verification steps involved in deploying clock gating and power gating in real-world chip design.

1. Introduction to Clock Gating and Power Gating

What Is Clock Gating?

Clock gating reduces dynamic power, which is caused by switching activity. It works by disabling the clock signal to specific registers or blocks when they are not actively processing data.

Dynamic Power Equation

Pdynamic=αCV2fP_{dynamic} = \alpha C V^2 fPdynamic=αCV2f

Clock gating reduces the activity factor (α) by eliminating unnecessary toggling.

What Is Power Gating?

Power gating reduces leakage power by completely turning OFF the power supply to unused logic blocks.

It is achieved by inserting power switches (header or footer cells) that isolate a block from VDD or GND.

Leakage Power Reduction Example

A typical power-gated block can reduce leakage by 50–95%, depending on technology node and usage.

2. RTL Implementation of Clock Gating

RTL clock gating is usually the first level of low-power optimization.

2.1 Types of RTL Clock Gating

1. a) Combinational Clock Gating

Simple AND/OR logic controls whether the clock is passed.

Example:

assign clk_gated = clk & enable;

However, this is not recommended because it causes glitches.

1. b) Integrated Clock Gating (ICG) Cells

Modern RTL uses ICG cells provided by the standard cell library.

Typical ICG consists of:

• A latch for glitch-free enable
• A clock gating element

RTL code style:

always @(posedge clk or negedge rst_n) begin

  if(!rst_n)

    state <= IDLE;

  else if (enable)

    state <= next_state;

end

Synthesis tools automatically map this to an ICG cell when:

• Enable is stable before clock edge
• No asynchronous logic is in the gating path

2.2 Auto-Clock Gating by Synthesis Tools

Tools like Synopsys Design Compiler or Cadence Genus can automatically infer clock gating based on coding style.

Guidelines for Auto-Inference

• Use if (enable) or if (valid) constructs
• Avoid unintentional latches
• Avoid mixing reset signals inside enable conditions
• Keep enable synchronous

2.3 RTL Guidelines for Clock Gating

• Always use synchronous enable signals
• Do not derive enable from the gated clock itself
• Use one enable signal for a group of registers (enable grouping)
• Avoid gating very small registers (wastes area and increases skew)
• Disable gating for high-fanout clock nets unless necessary

3. Backend Implementation of Clock Gating

Once clock gating is inserted at RTL, the backend flow must ensure physical correctness.

3.1 Placement of ICG Cells

Placement should:

• Keep ICG cells near the registers they drive
• Avoid long gated clock routes
• Reduce insertion delay and skew
• 
  

Backend tools perform clock tree synthesis (CTS) to balance both gated and ungated clock paths.

3.2 CTS Handling

Clock gating cells must be placed:

• In the leaf-level of the clock tree
• After balancing gated and ungated domains
• 
  

CTS compensates for:

• Added latency from the gating cell
• Additional setup time of the enable latch inside ICG

3.3 Physical Design Checks

Backend engineers must verify:

• No combinational logic exists after the ICG cell (only flop loads)
• Gated clocks are buffered appropriately
• Enable path meets timing (enable setup/hold checks)
• No glitch on ICG output

4. RTL Implementation of Power Gating

Power gating requires structural RTL partitioning and UPF (Unified Power Format) definition

.

4.1 Identifying Power Domains

Typical domains:

• Always-ON domain (AON)
• Switchable domain
• Retention domain

4.2 Retention Registers

When a block is powered off, important context needs to be retained.
Libraries provide retention flops with two power supplies:

• Regular VDD
• Retention VDD (always ON)

RTL must identify which registers need retention.

4.3 Isolation Cells

When a power domain turns OFF, its outputs must not float.
Isolation logic clamps signals to:

• Logic 0
• Logic 1
• Hold last value

RTL annotation example in UPF:

set_isolation iso_block -domain PD_SWITCH -clamp_value 0

4.4 Power Switch Control Logic

Control signals include:

• Sleep/Shutdown request
• Power good signal
• Isolation enable
• Retention save/restore

RTL must coordinate these signals through a Power Management Unit (PMU).

5. Backend Implementation of Power Gating

Power gating becomes more complex during physical design.

5.1 Inserting Power Switch Cells

Power switches can be:

• Header switches (PMOS between VDD and block)
• Footer switches (NMOS between GND and block)

PD engineers must determine:

• Number of switches based on IR drop
• Switch width and placement
• Grid connection strategy

5.2 Power-Gated Floorplan

Backend must ensure:

• Placement of isolation and retention cells near domain boundaries
• Proper routing of retention supply rails
• Dedicated stripes for power-gated rails
• Avoiding congestion due to switch cells

5.3 IR Drop and Wakeup Rush Current

When a block powers ON:

• High inrush current can cause voltage droop
• Staggered wake-up or switch sequencing is required

Tools like RedHawk or Voltus analyze:

• IR drop
• Electromigration
• Grid stability

6. Verification of Clock Gating

Verification is crucial to catch functional and low-power issues early.

6.1 Functional Verification

Check:

• Registers hold value when enable = 0
• State machines do not get stuck due to gated clocks
• No glitches in gated clock

6.2 Formal Verification

Equivalence checking (LEC) must:

• Map RTL to optimized gated netlist
• Validate no unintended gating inserted
• Ensure auto-clock gating is logically safe

6.3 Power-Aware Verification (UPF Simulation)

Verify:

• Clock gating works in low-power modes
• Enable signals maintain correct timing

7. Verification of Power Gating

Power-aware simulation with UPF is mandatory.

7.1 Power Gating Verification Checklist

Isolation Verification

• Outputs of off-domain must clamp
• No X-propagation to active blocks

Retention Verification

• Retention registers should save before power-off
• Restore sequence should match original state

Power Sequence Verification

Check complete power-down and wake-up flow:

1. Assert save signal
2. Enable isolation
3. Turn off switch
4. Power good → OFF
5. Wake-up request
6. Power switch ON
7. De-assert isolation
8. Restore retention state

UPF Checks

• Power domain connectivity
• Level shifter insertion correctness
• Retention power pins properly connected

7.2 Physical Verification

Backend must run:

• LVS/DRC with low-power rules
• Voltage-aware STA
• Multi-voltage ERC checks

Common Challenges and Best Practices

Clock Gating Challenges

• Late enable arrival causing timing failures
• Over-gating increases skew
• Clock-tree imbalance causing jitter

Power Gating Challenges

• Inrush current causing instability
• Incorrect isolation leading to X-propagation
• Retention flop failures due to UPF errors

Best Practices

• Use tools for auto-clock gating, but review manually
• Keep power domains as coarse-grained as possible
• Use STA with multi-voltage corners
• Verify all power modes (standby, sleep, retention, active)

Conclusion

Clock gating and power gating are indispensable low-power design techniques in modern SoC development. Implementing them correctly requires coordinated work across RTL design, synthesis, backend physical design, STA, and verification.

Clock gating primarily reduces dynamic power, while power gating significantly minimizes leakage power—together delivering substantial power savings. By following solid RTL coding practices, proper UPF modeling, careful physical planning, and exhaustive low-power verification, teams can build high-performance and energy-efficient silicon that meets modern power budgets.