Week 1–2: Foundation & Core Concepts (Day 1–14)

Goal: Understand the fundamentals of digital electronics and VLSI design.

Topics to Cover:

• Number systems, Boolean algebra, and logic gates

• Combinational and sequential circuits

• Flip-flops, multiplexers, encoders, decoders

• Introduction to VLSI – Moore’s Law, CMOS tech, IC fabrication

Suggested Free Resources:

• NPTEL: Digital Circuits by IIT professors

• All About Circuits (website) for basic digital theory

• Khan Academy – Boolean logic and flip-flops

YouTube Channels:

• VLSIFirst

Tasks:

• Daily concept notes (max 2 pages/day)

• Solve 10 MCQs daily from previous GATE or VLSI entrance papers

• Create a digital logic circuit using Logisim

Week 3–4: HDL Programming Basics (Day 15–28)

Goal: Learn VHDL/Verilog and basic simulation.

Topics to Cover:

• HDL introduction (choose Verilog or VHDL)

• Syntax, operators, modules, ports, always blocks

• Writing and simulating simple designs like full adders, counters, FSMs

Tools to Install:

• Icarus Verilog + GTKWave (Free & light-weight)

• EDA Playground (browser-based simulation platform)

• ModelSim (Student edition) – for deeper simulation practice

Paid Courses to Consider:

• VLSIFirst.com: “Verilog Essentials for Beginners” (hands-on lab access)

• Udemy: “Learn Verilog HDL from Scratch”
  
  

Practice Ideas:

• Daily mini HDL assignments

• Simulate 1–2 modules every 2 days

• Join Discord/Telegram groups for VLSI learners for peer support

Week 5–6: Synthesis & Static Timing Analysis (Day 29–42)

Goal: Transition from design to real-time synthesis & STA concepts.

Topics to Cover:

• RTL to gate-level synthesis flow

• Constraints (SDC), setup & hold time concepts

• Clocking and timing violations

• Basic STA commands (via Synopsys/Vivado)

Tools:

• Xilinx Vivado WebPack (Free for practice)

• Synopsys Design Compiler (if available via institute/partner access)

Practice Resources:

• VLSI First PDFs + LinkedIn learning tutorials

• Attend free STA workshops by industry mentors
  
  

Outcome:

• Simulate timing paths

• Analyze synthesis reports

• Understand where design fails timing and why

Week 7–8: RTL Projects + Intro to Physical Design (Day 43–56)

Goal: Apply HDL to real projects + peek into backend VLSI.

Suggested Projects:

• 8-bit ALU design

• UART transmitter/receiver

• Simple vending machine FSM

• Stopwatch or Timer using FSM logic

Tools:

• Use Vivado or EDA Playground for project simulation

• GitHub to document and publish your project portfolio

Learn Basics of Physical Design:

• Floorplanning, placement, clock tree synthesis (CTS), routing

• Tools like OpenLANE (open-source flow)

• Optional: “Intro to Physical Design” course on Udemy
  
  

Tip:

• Record simulation videos and share on LinkedIn with code snippets for visibility

Week 9–10: DFT, CMOS & Layout Concepts (Day 57–70)

Goal: Broaden your exposure and stand out in interviews.

Topics:

• Scan chains, DFT, ATPG basics

• CMOS inverter, stick diagrams, design rules

• Layout of NAND, NOR gates

• LVS/DRC intro

Practice Tools:

• Microwind or Magic VLSI for layout practice

• Online CMOS design simulators

• ASIC World for DFT practice questions

Paid Options:

• VLSIFirst workshops for layout + CMOS basics (includes doubt sessions)

Week 11–12: Resume, Mock Interviews, and Final Prep (Day 71–90)

Goal: Become placement-ready and confident for real opportunities.

Must-Haves in Your Resume:

• 2–3 Verilog mini-projects with simulation outputs

• Keywords like "Synthesis", "STA", "DFT basics", "Vivado", "RTL design"

• GitHub + LinkedIn profile with learning documentation

Templates:

• Use Novoresume or FlowCV to build a modern, ATS-friendly resume
  
  

Interview Prep:

• Revise basic questions on logic design, HDL syntax, FSM

• Practice GATE-level questions on timing, CMOS, and delay calculations

• Mock interviews via online communities or alumni mentors

Final Checklist:

• Join job portals like VLSIJobs and LinkedIn groups

• Target internships and entry-level jobs from Indian startups or Tier-2 companies in Bangalore, Hyderabad, Noida

• Keep practicing, even after 90 days—VLSI is a long journey but worth it

Tips for Success:

1. AI Meets VLSI: Start exploring how AI/ML is used in EDA tools.

2. Follow Industry News: Semiwiki, AnandTech, and Design&Reuse are good sources.

3. Stay Consistent: Even 2 focused hours a day is enough with the right structure.

4. Get Feedback: Post progress on LinkedIn and ask for feedback from VLSI seniors.

5. Learn Git: Knowing Git version control will help with project documentation and collaboration.

Final Thoughts

You don’t need to spend lakhs to learn VLSI. With the right blend of discipline, digital resources, and community support, you can go from beginner to job-ready in just 90 days. The semiconductor industry is booming, and skilled VLSI engineers are in high demand across domains like AI chips, automotive SoCs, and edge devices.

So, grab your notebook, power up your laptop, and start building your VLSI future today—90 days from now, you'll be amazed at how far you've come.