ASIC Design in noida

• Number Systems and conversions
• Number System complements (Binary Arithematics - Addition and Subtraction)
• Boolean algebra, Boolean theorems and laws, Sum of products and product of sums, Minterms and Maxterms
• Karnaugh map Minimization
• Logic gates, Enable & disable concept of gates, Tristate logic gates
• Binary Codes – Binary, BCD, Excess 3, Gray
• Error detection & correction - Parity method
• Hazards in combinational circuits
• Half Adder, Full Adder, RCA
• Multiplexer, Demultiplexer
• Encoders, Priority Encoders
• Decoder (Active high & low outputs), Magnitude Comparator
• Sequential circuits: Latches (SR Latch, S'R' latch), gated latch (SR, D latch)
• Clock - Triggering types, clock duty cycle, clock jitter, glitches & skew
• Sequential circuits: Flipflops & types (characteristic and excitation tables)
• Master/Slave FF – Operation, timing diagrams
• Shift registers - SISO, SIPO, PISO, PIPO
• Shift registers - Universal Shift Register, Bidirectional
• Design of Counters- Asynchronous Counters - Up, Down, Up-Down counters, Ring Counter, Jhonson counter
• Synchronous Counters - Up, Down, Up-Down counters
• Clock generation, Setup time, Hold time, Metastability and frequency calculations, frequency division using counters
• State Machines Design – Moore models (Overlapping & Non Overlapping)
• Mealy models (Overlapping & Non Overlapping)
• Memory structure - ROM/ RAM
• Synchronous FIFO
• Asynchronous FIFO

• Linux Commands
• How to work with Gvim Editor Tool
• Shortcuts & Tricks

• Introduction to HDL
• Differences b/w high level language (C Programming) and HDL, VHDL vs Verilog HDL, VLSI Design Flow cycle.
• Introducing RTL Design (DUT) and Testbench
• Defining RTL Design (DUT) and Verilog Testbench, Structure of DUT and Verilog Testbench.
• What are Ports and types?
• What is Instantiation?
• Compilation vs Simulation vs Synthesis
• Modelling Styles-Levels of Abstraction
• Data Flow Modelling- Implicit Continuous Assignments
• Tool Introduction with basic gates or MUX example in Dataflow modelling along with TB
• Basic Concepts- Lexical Conventions (White Spaces, Comments, Operators, Number Specifications, Strings, Keywords, Identifiers)
• Data Types (Net Data Types, Register Data Types), System Tasks, Defines, Parameters, timescale
• Operators (Concatenation, Replication, Negation, Unary Reduction, Arithmetic, Shift, Relational, Equality Logical, Case, Bit-wise, Logical-wise, Conditional)
• Modelling Styles- Gate Level Modelling- Gate Level Primitives (and, or, nand, nor, xor, xnor, not)
• Structural Modelling-Instantiation- Naming, Positioning, Example-Ripple Carry Adder
• Behavioural Modelling- Procedural Blocks- initial and always, Sensitivity list, Blocking assignments/statements
• Behavioural Modelling- Non-blocking assignments/statements, Inter and Intra Delays
• Verilog Stratified Queues (Verilog Regions)- Active, Inactive, NBA, Monitor/Postponed Regions
• Behavioural Modelling- If-else (2x1 and 4x1 Mux), case, casex, casez (4x1 Mux, Priority Encoder)
• Behavioural Modelling- Looping Statements- for, repeat, while, forever, begin-end, fork-join, naming of blocks, disable
• Verilog Functions- Introduction, formal arguments, actual arguments, function call, example- Ripple Carry Adder
• Verilog Tasks- Introduction, example- Ripple Carry Adder, Task based Testbench
• Verilog Coding- Arrays, Memories (ROM)
• Verilog Coding- Memories (RAM)
• Verilog Coding- Finite State Machines (Moore, Mealy -- Overlap, Non-overlap)
• Verilog Coding- Synchronous FIFO

• Testbench approaches - Self checking testbench, Linear TB, Random TB
• Compiler Directives ('ifdef, 'ifndef, 'endif, 'else)
• $value$plusargs, Force-Release, ceil, log
• Clock generation and frequency calculations, frequency division using counters, clock duty cycle
• File Handling's in verilog, PLI 
• Generate block - Genvar Keyword, Specify block and UDP

• Introduction to RTL Linting
• Objectives and Benefits of Linting
• Overview of SpyGlass Lint Rules
• Common Lint Targets and Use Cases
• Understanding the lint_rtl Goal
• SpyGlass Lint Flow and Environment Setup
• Detailed Review of SpyGlass Lint Rule Categories
• Typical RTL Lint Targets
• Design Reading and Preparation for Lint
• Goal Configuration and Setup
• Running Lint Analysis and Debugging Violations
• Hands-On Lint Example
• Basic concepts of Static Timing Analysis
• Introduction to Clock Domain Crossing (CDC)
• Understanding Clock Domains and Clock Grouping
• Fundamentals of Synchronous Digital Design
• CDC Synchronization Methods and Architectures
• Common CDC Issues and Recommended Solutions
• CDC Flow Challenges: Single-Bit vs. Multi-Bit Crossings
• Handling Burst Data Transfers Across Clock Domains
• Using Constraints vs. Waivers in CDC Analysis
• Capturing Design Intent Through CDC Constraints
• SpyGlass CDC Setup and Tool Flow
• Running CDC Analysis and Debug Steps

• Introduction of System Verilog
• Necessity to migrate from Verilog --> SV --> UVM
• Limitations of Verilog HDL
• Role of Verification
• Types of Verification (Functional/Formal/AMS)
• Verification Plan Document (Vplan or VPD)
• Architecture of SV Environment
• New Data types introduced in SV – Enum, Typedef, Structure, Union, Class
• Arrays - Fixed Array (Packed and Unpacked), Dynamic Array, Associative Array
• Queues & Queue methods
• Loops - Enhanced for loop, foreach loop, while loop, dowhile loop, repeat, forever
• Procedural Statements and Flow Control - Conditional statements (unique if, priority if, unique case, priority case), jump statements, statement labels, disable statements, new procedural blocks (always_comb,always_latch,always_ff,final)
• Sub routines – Functions & Task
• Interface, Modports, clocking block
• SV Regions
• Assertions - Assertion Based Verification (ABV), Need and Types of Assertions, Immediate Assertion, SVA Building Blocks, Concurrent Assertions, Assertions Built-in methods, SVA Binding 
• SV TB Environment

All the projects delivered are as per industry standard implementations of High speed protocols/Memories/RISC-V/Interconnects

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