Design and Verification in pune

• Number Systems and conversions
• Number System complements (Binary Arithematics - Addition and Subtraction)
• Boolean algebra, Boolean theorems and laws, Sum of products and product of sums, Minterms and Maxterms
• Karnaugh map Minimization
• Logic gates, Enable & disable concept of gates, Tristate logic gates
• Binary Codes – Binary, BCD, Excess 3, Gray
• Error detection & correction - Parity method
• Hazards in combinational circuits
• Half Adder, Full Adder, RCA
• Multiplexer, Demultiplexer
• Encoders, Priority Encoders
• Decoder (Active high & low outputs), Magnitude Comparator
• Sequential circuits: Latches (SR Latch, S'R' latch), gated latch (SR, D latch)
• Clock - Triggering types, clock duty cycle, clock jitter, glitches & skew
• Sequential circuits: Flipflops & types (characteristic and excitation tables)
• Master/Slave FF – Operation, timing diagrams
• Shift registers - SISO, SIPO, PISO, PIPO
• Shift registers - Universal Shift Register, Bidirectional
• Design of Counters- Asynchronous Counters - Up, Down, Up-Down counters, Ring Counter, Jhonson counter
• Synchronous Counters - Up, Down, Up-Down counters
• Clock generation, Setup time, Hold time, Metastability and frequency calculations, frequency division using counters
• State Machines Design – Moore models (Overlapping & Non Overlapping)
• Mealy models (Overlapping & Non Overlapping)
• Memory structure - ROM/ RAM
• Synchronous FIFO
• Asynchronous FIFO

• Linux Commands
• How to work with Gvim Editor Tool
• Shortcuts & Tricks

• Introduction to HDL
• Differences b/w high level language (C Programming) and HDL, VHDL vs Verilog HDL, VLSI Design Flow cycle.
• Introducing RTL Design (DUT) and Testbench
• Defining RTL Design (DUT) and Verilog Testbench, Structure of DUT and Verilog Testbench.
• What are Ports and types?
• What is Instantiation?
• Compilation vs Simulation vs Synthesis
• Modelling Styles-Levels of Abstraction
• Data Flow Modelling- Implicit Continuous Assignments
• Tool Introduction with basic gates or MUX example in Dataflow modelling along with TB
• Basic Concepts- Lexical Conventions (White Spaces, Comments, Operators, Number Specifications, Strings, Keywords, Identifiers)
• Data Types (Net Data Types, Register Data Types), System Tasks, Defines, Parameters, timescale
• Operators (Concatenation, Replication, Negation, Unary Reduction, Arithmetic, Shift, Relational, Equality Logical, Case, Bit-wise, Logical-wise, Conditional)
• Modelling Styles- Gate Level Modelling- Gate Level Primitives (and, or, nand, nor, xor, xnor, not)
• Structural Modelling-Instantiation- Naming, Positioning, Example-Ripple Carry Adder
• Behavioural Modelling- Procedural Blocks- initial and always, Sensitivity list, Blocking assignments/statements
• Behavioural Modelling- Non-blocking assignments/statements, Inter and Intra Delays
• Verilog Stratified Queues (Verilog Regions)- Active, Inactive, NBA, Monitor/Postponed Regions
• Behavioural Modelling- If-else (2x1 and 4x1 Mux), case, casex, casez (4x1 Mux, Priority Encoder)
• Behavioural Modelling- Looping Statements- for, repeat, while, forever, begin-end, fork-join, naming of blocks, disable
• Verilog Functions- Introduction, formal arguments, actual arguments, function call, example- Ripple Carry Adder
• Verilog Tasks- Introduction, example- Ripple Carry Adder, Task based Testbench
• Verilog Coding- Arrays, Memories (ROM)
• Verilog Coding- Memories (RAM)
• Verilog Coding- Finite State Machines (Moore, Mealy -- Overlap, Non-overlap)
• Verilog Coding- Synchronous FIFO
• Modelling Styles- Switch Level Modelling- PMOS, NMOS, CMOS- NOT, NAND, NOR, AND, OR Gates (optional)

• Testbench approaches - Self checking testbench, Linear TB, Random TB
• Compiler Directives ('ifdef, 'ifndef, 'endif, 'else)
• $value$plusargs, Force-Release, ceil, log
• Clock generation and frequency calculations, frequency division using counters, clock duty cycle
• File Handling's in verilog, PLI (optional)
• Generate block - Genvar Keyword, Specify block and UDP (optional)

• Importance of Verification
• Difference b/w Design & Verification
• Difference b/w HDL & HVL
• Challenges in Verification
• Verification Flow
• Roles & Types in Verification
• Difference Verilog & System Verilog
• Why System Verilog prefered over verilog
• Functional Verification vs Formal Verification

• Introduction of System Verilog
• Necessity to migrate from Verilog --> SV --> UVM
• Architecture of SV Environment
• Data types - Enum, Typedef, Structure, Union, Class
• Arrays - Fixed Array (Packed and Unpacked), Dynamic Array, Associative Array, Queues
• Array methods - ordering, reduction, locator, index querying methods
• loops - Enhanced for loop, foreach, while, dowhile, repeat,forever
• Procedural Statements and Flow Control - Conditional statements (unique if, priority if, unique case, priority case)
• jump statements
• statement labels
• disable statements
• new procedural blocks (always_comb,always_latch,always_ff,final)
• Process control - fork_join, fork_join_any, fork_join_none, wait fork and disable fork
• Class - Nested/Aggregated class
• SV subroutines - Function & Task, Argument types and Argument Passing Types, Static and Automatic Methods
• Randomization - Why Randomization?, rand and randc keywords , Randomization methods, Randomization of scope variables, How to disable Randomization, How we can control Randomization
• Constraints - Inline, inside, unique, soft, Implication, weighted, static and iterative, function inside constraint, bi-directional and solve before
• Shallow copy & Deep Copy
• Interprocess communication - Semaphore, Mailbox, Events and wait_order
• OOPS - Inheritance, Constraint Inheritance, Casting (static & Dynamic), Data hiding and Encapsulation, Abstract Class, Polymorphism, Pure Virtual Methods, Parameterized class & typedef class
• Interface -Modports, Clocking Block, Program Block
• SV regions
• SV Environment with all the components
• Introduction to Coverage Driven Constraint Random Verification (CDCRV)
• Types of Coverages (Code & Functional)
• Brief about Functional Coverages
• Coverage Bins (Implicit & Explicit)
• Different types of bins (Transition, Binsoff, intercept)
• Conditional Coverage
• coverage options
• Introduction to Assertion Based Verification (ABV)
• Need and Types of Assertions
• Immediate Assertion"
• SVA Building Blocks
• Introduction to Concurrent Assertions
• Assertions Built-in methods
• SVA Binding

• User defined macros
• SV Packages
• Introducing DPI

• Verification Plan Document or V Plan
• Verification Architecture
• Feature Extraction and creating Test plan
• Coverage Plan
• Assertion Plan

• FIFO SV-TB Development

Introduction to Methodology

• What is UVM?
• Why UVM?
• Overview of UVM Structure.

UVM Testbench Architecture

• Test Bench Structure
• Explanation of Test Bench
• UVM Objects and UVM Components
• UVM Sequence Item
• UVM Sequence and UVM Sequencer
• UVM Driver and UVM Monitor
• UVM Agent and UVM Scoreboard
• UVM Test and UVM Top.

UVM Phases

• Types of Phases
• Explanation of Phases

UVM TLM

• Analysis Port
• Usage of TLM Ports
• Declaration and Connection of Ports

UVM Reporting

• Reporting Methods
• Configurations
• Usecases

UVM Configurations

• Usage of Configurations
• Set Config Methods

UVM Factory

• Registration
• Factory Methods Explanation

UVM Callback

• Body Call back
• Usage and Importance of Call Backs

Sequences

• Overview and Implementation of Sequences.

UVM Macros

• Macros Explanation in UVM.

UVM Project

• UVC Development for Industry standard protocol.
• Explanation of IP, VIP, SOC Level Testbench flow, Testplans, Verification plan.

Register Layer

• Introduction
• Register Model
• Register Environment
• Connection of Register Environment

Lock Grab

• Examples
• Arbitration
• Importance of Arbitration
• Usage of Arbitration
• Sequencer Arbitration
• Virtual Sequence, Sequencer
• Need and Usage of Virtual Sequence and Sequencer.

• Understanding APB Protocol
• Developing UVM environment for APB
• Developing Test cases

1. RTL Design Project based on Verilog
2. Verification Project based on UVM

All the projects delivered are as per industry standard implementations of High speed protocols/Memories/RISC-V/Interconnects

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