• Dataflow Modelling – continuous assignment statements
• Gate Level Modelling/Structural modelling
• Behavioural Modelling – Procedural blocks, procedural block statements – blocking and non-blocking assignments.
• Switch Level Modelling – switch primitives

• Latch – Definition, usage, types, Coding and Simulation Result Explanation.
• Flipflop – Types (dff, tff, jkff), Coding and Simulation Result Explanation, Sync and Async FF. Difference between Latch and Flipflop, Why Nonblocking should be used for Sequential Circuits?
• Counter - Both Synchronous and Asynchronous, Mod Counters, Repeated Counters, Ring, Johnson Counters.
• FSM – Melay and Moore, Timescale, Parameter, Local Param, ifdef
• Shift registers – SISO,PISO,PIPO,PISO, Bi-directional Registers, Universal Shift Registers
• MEMORIES – RAM, ROM, Frequency Dividers, Self-checking testbenches.

• Introduction & Importance
• Verification Methodologies
• System Verilog: Introduction to Verification and System Verilog.

• Integer, Void
• String, Event
• User-defined Enumerations
• Class Arrays
• Fixed Size Arrays - Packed and Un-Packed
• Dynamic Array - Associative Array, Queues, structure, Union, typedef

• always_ff, always_comb, Blocking & Non-Blocking assignments
• Unique-I, Priority-If
• While, do-while, for each & enhanced for loop
• Repeat, Forever
• Break & Continue
• Named Blocks and Statement Labels
• Disable block and disable statements
• Event Control.

• Tasks
• Functions
• Argument passing – Automatic, Static

• fork-join
• fork-join any
• fork-join none
• wait-fork
• disable-fork

• Classes
• This Keyword
• Constructors
• Static Class Properties & Methods
• Class Assignment
• Shallow Copy & Deep Copy
• Parameterized Classes
• Inheritance
• Overriding Class Members
• Super Keyword
• Polymorphism, Casting
• Data Hiding and Encapsulation
• Abstract Classes & Virtual Methods
• Class Scope Resolution Operator
• Extern methods
• Type def Classes.

• Constraint Blocks
• External Constraint Blocks
• Inheritance
• Inside operator
• Weighted distribution
• Implication and if-else and other constructs.

• Scheduling Semantics
• Program Block
• Interface
• Mod port
• Clocking Blocks.

• Assertions
• SVA Building Blocks
• SVA Sequence
• Implication Operator
• Repetition Operator
• SVA Built in Methods
• Ended and Disable iff.

• Coverage
• Functional Coverage – Types
• Coverage Options - Parameters and define.

INTRODUCTION

• What is UVM?
• Why UVM?
• Overview of UVM Structure.

UVM Testbench Architecture

• Test Bench Structure
• Explanation of Test Bench
• UVM Objects and UVM Components
• UVM Sequence Item
• UVM Sequence and UVM Sequencer
• UVM Driver and UVM Monitor
• UVM Agent and UVM Scoreboard
• UVM Test and UVM Top.

UVM Phases

• Types of Phases
• Explanation of Phases

UVM TLM

• Analysis Port
• Usage of TLM Ports
• Declaration and Connection of Ports

Register Layer

• Introduction
• Register Model
• Register Environment
• Connection of Register Environment

UVM Reporting

• Reporting Methods
• Configurations
• Usecases

UVM Configurations

• Usage of Configurations
• Set Config Methods

UVM Factory

• Registration
• Factory Methods Explanation

UVM Callback

• Body Call back
• Usage and Importance of Call Backs

Lock Grab

• Examples
• Arbitration
• Importance of Arbitration
• Usage of Arbitration
• Sequencer Arbitration
• Virtual Sequence, Sequencer
• Need and Usage of Virtual Sequence and Sequencer.

Sequential and Parallel Sequence, Layered Sequences

• Overview and Implementation of Sequences.

UVM MACROS

• Macros Explanation in UVM.

UVM Project

• UVC Development for Industry standard protocol.
• Explanation of IP, VIP, SOC Level Testbench flow, Testplans, Verification plan.