Understanding the ASIC Design Flow: Key Steps Followed

  • April 23, 2024

    author: Ramya

Application-Specific Integrated Circuits (ASICs) are essential in the world of electronics for enabling complicated functionality for a variety of applications. ASIC design uses a methodical process to convert requirements into a unique integrated circuit. This blog attempts to give readers a thorough grasp of the ASIC design flow, highlighting both the most important processes and the difficulties encountered along the way.

1. Specification and Architecture: A comprehensive understanding of the project requirements and specifications is a prerequisite for the ASIC design process. It entails specifying the system's functionality, performance objectives, power limitations, and other factors. To guarantee alignment between the design team and the client, it is essential to accurately record and comprehend the requirements. Managing changing specifications and finding the ideal balance between capability and restrictions provide challenges in this situation.

Recognizing the Conditions: Understanding the project requirements in its entirety is the first stage in the ASIC design flow. This entails working together with the client or other project stakeholders to compile data on the functionality that is desired, performance objectives, power limitations, and other system-level issues.

Architectural Design: Following the collection of the requirements, the architectural design of the ASIC is defined. Choosing the circuit's overall structure and organization, including the choice of functional blocks, interconnections, and interfaces, is required for this.

Before moving on, a feasibility analysis is done to determine the practicality of the suggested architecture. This analysis takes into account a number of variables, including the accessibility of necessary IP (intellectual property) blocks, technological limitations, expected cost, and timeline.

Performance Estimation: Performance estimation is essential during the specification and architectural design phases. Designers evaluate the ASIC's performance using a variety of methodologies, including simulations, analytical models, and prototypes.

Performance estimation is not the only crucial step in the design process; power and area estimation are also essential. The process of power estimation entails examining the ASIC's power usage under various operating circumstances. It aids in locating power-hungry components and improving how power is distributed throughout the architecture.

Architectural design and specification both entail creating numerous design restrictions. These limitations include those related to manufacturing, signal integrity, power limits, and timing requirements. The difficulty here is to precisely and completely specify the limitations.

Iterative Refinement: An iterative refinement technique is frequently used during the stages of specification and architectural design. Iterations are done to improve the design's effectiveness and functionality as the design team learns more about the specifications and considers architectural options.

 Design entrance: The design entrance stage starts when the specifications are established. To generate a high-level representation of the ASIC, designers use hardware description languages (HDLs) like Verilog or VHDL. The functionality and linkages between the different components are described in this model. The difficulty for designers is to create an accurate and effective design that satisfies the requirements while retaining a tolerable level of complexity.

The initial choice in the design entry phase is the Hardware Description Language (HDL) that will be used for the ASIC design. The most widely used languages in the sector are Verilog and VHDL.

Writing the Register Transfer Level (RTL) Code: After choosing the HDL, designers write the RTL code. RTL is a level of hardware description that depicts the behavior and relationships of different design elements.

RTL Synthesis Synthesis of the Register Transfer Level (RTL) is a crucial phase of the ASIC design process. It entails leveraging a library of common cells to translate the high-level design into a gate-level representation. During this procedure, optimizations are used to accomplish the goals of area, power, and timing. It can be difficult to strike a balance between these optimization aims because over-optimization in one area can compromise other others.

Functional Verification: Before moving on, it's crucial to make sure the design is proper. By generating and running test cases, functional verification includes testing the ASIC's behavior. The goal of the verification process is to make sure that the design operates as intended under a variety of input circumstances. It might be difficult to achieve thorough verification coverage since it calls for a careful selection of test cases and thorough simulation to look for probable design flaws or functional problems.

Design planning comprises floorplanning, which establishes the location of various design elements on the chip. It takes into account factors like timing, power distribution, and physical design limitations. Finding an ideal floorplan that minimizes signal delays, lowers power consumption, and satisfies the stipulated area limitations is the difficult part of design planning. Iterative refining and cautious trade-offs are needed to balance these factors.

Physical Design: Detailed implementation tasks, including as location, routing, and temporal closure, are included in the physical design stage. Routing establishes the actual connections between each component on the device while placement determines its precise location on the chip. Timing closure makes ensuring the design achieves the necessary performance goals. Physical design has substantial obstacles due to the complexity of large systems, the optimization of power usage, and the achievement of timing closure.

Design testing: After the physical design is finished, the ASIC goes through additional testing to make sure it is proper and adheres to standards. Static timing analysis, formal verification, and simulation-based testing are just a few of the methods used. Finding and fixing any design flaws that were introduced during the physical design phase presents a problem in this situation. This is a crucial and time-consuming process because to the intricacy of the design and the requirement for thorough verification.

Design Approval: The design goes through a signoff process before being manufactured after successfully completing the verification step. The signoff confirms that the design is complete and satisfies all requirements before it can be put into production. Final checks, such as design rule checks (DRC) and electrical rule checks (ERC), are required in this to guarantee adherence to production standards. The difficulty is in ensuring that the design is devoid of any significant flaws that can impair functioning or ease of manufacture.


The key phases in creating a unique integrated circuit were outlined in this blog post's detailed description of the ASIC (Application-Specific Integrated Circuit) design cycle.Understanding the ASIC design flow is crucial for producing effective custom integrated circuits because it offers a methodical strategy for overcoming the complexity and difficulties involved in ASIC design.Designers can confidently move through the ASIC design flow by adhering to the essential processes described in this blog, resulting in the production of high-quality, optimised, and functioning ASICs that satisfy the intended specifications and performance criteria